LPonTR 2011 - Call for Papers

CALL FOR PAPERS

Scope -- Submissions -- KeyDates -- Additional Information -- Committees

Scope

The IEEE InternationalWorkshop on Impact of Low Power Design on Test and Reliability (LPonTR) aims to bring together design, reliability and test engineers and researchers to discuss the impact of advanced low-power low-voltage design methodologies of nanometer silicon systems on test and reliability. Power and thermal issues, leakage, process variations, susceptibilityto environmental and operation-induced interference drive the development of low-power, process-tolerant design techniques and generate a new set of test and reliability challenges, questing for an innovative set of methodologies and tools.

You are invited to participate in LPonTR’11 by presenting work that addresses current trends, challenges and solutions in the following areas (but are not limited to:

Energy-reliability radeoff (inc. controlled losses) and its integration with power management
Power and Thermal Issues in 3D ICs
Challenges of UltraLowpower design on test and reliability
Emerging failure modes
Test of SoC with power and thermal management
Energy, power and process variations aware design and test
Test and reliability implications of leakage
Low-power/voltage DfT, Dynamic BIST, Scan and ATPG
Delay, statistical nd parametric testing for LP circuits
Signal integrity under test
Test and reliability of LP redundant systems
Analog, mixed-signal and asynchronous low-power design, test and DfT
EDA tools to support process-tolerant LP design

Special Sessions:

“Adaptive Techniques for Energy-Reliability Trade-offs” (chaired by I. Polian) – discussion of methods which lead to significant energy savings at the expense of controlled losses in accuracy and reliability of the calculated data; implications on he design flow.
“Power and Thermal Issues in 3D ICs” (chaired by G. Jervan) – impact of power consumption and heat dissipation on the performance and reliability of 3D SoC, which includes (but not limited to) power/thermal modelling and analysis,power/thermal-aware design, power integrity, heat dissipation, thermal vias, thermal/mechanical stress and cooling mechanisms.

Submissions

top

Submissions – The authors are invited to submit extended abstracts. All submissions will be peer reviewed and accepted abstracts will be published in the informal proceedings f the workshop.

Presentations – Full oral presentations are 15-20 min., short oralare 2 min. There will be space provided for tool demonstrations and poster/interactive presentations.

Journal Publications – The best contributions will be invited for ublication as full papers in a Special Section on LPonTR’11 in the ASP Journal of Low Power lectronics (JOLPE).

Formats – extended abstracts: 2 pages, IEEE conference layout or latex8, font 10, two columns, paper A4, no page numbering, PDF file format.
Posters: up to A0-portrait. Format for demonstrations: please contact the Chairs.

Communication – Please e-mail your manuscripts directly to the Chairs ofLPonTR.

Key Dates

top

Submission deadline: March 21, 2011
Notification of acceptance: April 12, 2011
Final copy deadline: May 10, 2011

Additional Information

top

Dr. Alex Bystrov
Newcastle University
School of EECE
Newcastle upon Tyne, NE1 7RU, UK
Tel.: +44 191 222 6584
Fax: +44 191 222 8180
Email: A.Bystrov@ncl.ac.uk

Dr. Patrick Girard
LIRMM
161 rue Ada,
34392 Montpellier cedex 05, France
Tel.: +33 467 418 629
Fax.: +33 467 418 500
Email: girard@lirmm.fr

Committees

top

Chair / Co-Chair
Alex Bystrov, Newcastle Univ., UK
Patrick Girard, LIRMM, France

Special Session Chairs
Ilia Polian, Univ. Freiburg, Germany
Gert Jervan, Tallinn Univ., Estonia

Programme Committee
Bashir Al-Hashimi, Univ. of Southampton, UK
Karim Arabi, Qualcomm, USA
Swarup Bhunia, Case Western Reserve Univ., USA
Krish Chakrabarty, Duke Univ., USA
Krishna Chakravadhanula, Cadence, USA
Luigi Dilillo, LIRMM, France
Peter Harrod, ARM Ltd, UK
Mokhtar Hirech, Synopsys, USA
Gert Jervan, Tallinn Univ., Estonia
Niraj Jha, Princeton University, USA
Mark Kassab, Mentor Graphics, USA
Sandip Kundu, Univ. Massachusetts, USA
Erik Larsson, Linkoping Univ., Sweden
T.M. Mak, Intel, USA
Hans Manhaeve, Q-Star, Belgium
Nicola Nicolici, McMaster Univ., Canada
Ilia Polian, Univ. Freiburg, Germany
Irith Pomeranz, Purdue Univ., USA
Srivaths Ravi, TI, India
Sudhakar Reddy, Univ. of Iowa, USA
Juan Jose Rodriguez Andina,
Univ. Vigo, Spain
Ozgur Sinanoglu, Univ. NYUAD, Abu Dhabi
Virendra Singh, Indian Institute of Science, India
Mohammad Tehranipoor, Univ. Connecticut, US
J. Paulo Teixeira, INESC-ID, Portugal
Nur Touba, Univ. of Texas at Austin, USA
Seongmoon Wang, NEC, USA
Xiaoqing Wen, Kyushu Inst. of Technology, Japan
Hans-Joachim Wunderlich, Univ. of Stuttgart, Germany
Qiang Xu, The Chinese University of Hong Kong

For more information, visit us on the web at: http://www.staff.ncl.ac.uk/a.bystrov/LPonTR/

The 4th IEEE International Workshop on Impact f Low-Power design on Test and Reliability (LPonTR 2011) is sponsored by he Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).